`timescale	1ns/1ns
module remote_sys(
input	wire		sclk,
input   wire            reboot_en
);
reg     [14:0]   reset_cnt;

always @(posedge sclk)
        if(reset_cnt[14])
                reset_cnt<='d0;
        else if(reboot_en=='d0)
                reset_cnt<=reset_cnt+'d1;

		
rsu_base	rsu_base_inst (
	.clock ( ),
	.data_in ( ),
	.param (  ),
	.read_param ( ),
	.read_source (  ),
	.reconfig ( ),
	.reset ( ),
	.reset_timer ( reset_cnt[13] ),
	.write_param (  ),
	.busy (  ),
	.data_out (  )
	);

endmodule